1. Field of the Invention
The present invention relates generally to the field of programmable computer processors, and more particularly to programmable logic configuration for instruction extensions.
2. Description of the Prior Art
Computer processors can generally be sorted into two classes: general purpose processors that can be adapted to a multitude of applications; and application-specific processors that are optimized to serve specific applications. General purpose processors are designed to run a general instruction set, namely a set of instructions that the processor will recognize and execute. Such general instruction sets tend to include a large number of instructions in order to support a wide variety of programs.
Application-specific processors are designed to run a more limited instruction set, where the instructions are more tailored or specific to the particular application. While an application-specific processor can enable certain programs to execute much faster than when run on a general purpose processor, they are by definition more limited in functionality due to the limited instruction sets they run.
Before the application-specific processor is manufactured, instructions may be added to extend the application-specific processor's instruction set. In one example, instructions may be added using a Tensilica Instruction Extension (TIE) language and a TIE compiler from Tensilica, Inc. of Santa Clara, Calif. A designer defines the new instruction in the TIE language by specifying the characteristics of the instruction such as the field, the opcode, and the operands. A TIE compiler then compiles the source code in the TIE language for the new instruction for simulation, verification, and creation of the necessary files such as dynamic linked libraries.
One problem with the TIE language and the TIE compiler is that instructions can only be added prior to the fabrication of the processor. This time period before fabrication is also known as “pre-silicon.” The time period after fabrication is known as “post-silicon.” One problem with the TIE language and the TIE compiler is the instruction set of the processor cannot be extended to include new instructions during this post-silicon period. Furthermore, another problem with the TIE language and the TIE compiler is during this post-silicon period, the characteristics of the instructions cannot be changed or modified. Therefore, during this post-silicon period, the processor is limited only to a finite set of instructions defined in the pre-silicon period and limited to the characteristics of the instructions defined in the pre-silicon period.
Some systems have used programmable logic devices (PLD) with processors. One example of a programmable logic device is a field-programmable gate array (FPGA). One prior art system called Garp includes a MIPS processor with reconfigurable hardware that are both located on the same die. This Garp system uses a co-processor model of communication between the processor and the reconfigurable array. The reconfigurable hardware in this Garp system is an FPGA that acts as a slave computational unit to the MIPS processor, where the MIPS processor would explicitly hand control to the reconfigurable array and wait until the array task is completed. Although the reconfigurable array and the MIPS processor share a common path to a cache and memory, there is no direct connection between the processor's data path and the array. This Garp system is described in a publication entitled “Garp: A MIPS Processor with a Reconfigurable Coprocessor” by John R. Hauser and John Wawrzynek.
One example of an FPGA is manufactured by Altera in San Jose, Calif. Another example of an FPGA is a Virtex-II Pro (V2Pro) FPGA manufactured by Xilinx in San Jose, Calif. This V2Pro FPGA uses a more loosely coupled model of communication in which the FPGA appears as a memory mapped peripheral to the processor(s).
One problem with the Garp system and the V2Pro FPGA is the cost of initiating a computation in the programmable fabric. In both the Garp system and the V2Pro FPGA, the processor must execute several instructions to initiate a co-processor computation, which adds overhead to initiate an extension instruction. Also, the processor must wait for the co-processor computation to complete, which prevents other instructions from being executed.
Accordingly, what is desired is the ability to write a program in a convenient programming language and to extend an instruction set of a computer processor with instructions tailored to that program so that the program can execute on that computer processor more efficiently.